Quite often after Fault Localization like OBIRCH or Photon Emission there it is the need to have a detailed look at the layers underneath the surface of the chip. We can perform FIB cross sectioning to achieve this but in that case we need very accurate fault localization as well as navigation capabilities in the DualBeam FIB/SEM. Optical Microscopy might be an option but it will only show irregularities in the top metal layer of the chip. The underlaying metal layers are optically blocked by the ones on top.
Front Side deprocessing
We can accurately grind/polish down the layers on top one by one to achieve good sight on the feature of interest. Additional Optical, SEM microscopy or both can be applied to obtain the best images of the failure location. Quite often the sample is still suitable for FIB cross section or even TEM analysis. For example for TEM analysis in a memory region it is required to remove the top metal layers just to navigate to there right column and row.
We can also prepare your sample for transistor characterization measurements. This means we polish the sample down till contact level. This way you will be able to measure suspicious transistors using nano probe equipement.
This technique is used to obtain high resolution images of the backside. For example to determine if the gate oxide is still good or to see the physical gate length or just to get a function block layout. In a nutshell what we do is take the chip and put it upside down and remove all the bulk silicon. This can be a thin chip with a thickness of 75 µm but we can also deal with chips with full wafer thickness of 700 µm. When all the bulk silicon is removed we can have a detailed look at the STI Shallow Trench Isolation and GateOxide .
In case electrical characterization and OBIRCH fault localization is performed you may want to proceed with DFA Destructive Failure Analysis. Quite often backside preparation is performed to obtain quick and the most detailed images of the failure. This can be subtle pinholes in the gateoxide but also EOS Electrical Over-Stress signatures between transistor junctions.
For competitor analysis purpose backside analysis is a quick and low cost way to obtain a lot of information of the chip. Like for example what is the functional block layout or the process node of the chip.
- Technology node determination of the latest Integrated Circuits
- Gate oxide defects inspection like pinholes
- Reverse Engineering to get smooth functional block layout
- EOS events in the FEOL
Please contact us in case you like to have your chips deprocessed.More Services: SEM-EDX, Chip Deprocessing, FIB cross sectioning, OBIRCH, HR-TEM, STEM-HAADF, FIB Circuit Edit, Failure Analysis, Photon Emission